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ltc4263 1 4263fe typical application features applications description single ieee 802.3af compliant pse controller with internal switch the ltc ? 4263 is an autonomous single-channel pse controller for use in ieee 802.3af compliant power over ethernet systems. it includes an onboard power mosfet, internal inrush, current limit, and short-circuit control, ieee 802.3af compliant pd detection and classi? cation circuitry, and selectable ac or dc disconnect sensing. onboard control algorithms provide complete ieee 802.3af compliant operation without the need of a microcontroller. the ltc4263 simpli? es pse implementation, needing only a single 48v supply and a small number of passive support components. programmable onboard power management circuitry permits multiple ltc4263s to allocate and share power in multi-port systems, allowing maximum utilization of the 48v power supplyall without the intervention of a host processor. the port current limit can be con? gured to automatically adjust to the detected pd class. detec- tion backoff timing is con? gurable for either endpoint or midspan operation. built-in foldback and thermal protection provide comprehensive fault protection. an led pin indicates the state of the port controlled by the ltc4263. when run from a single 48v supply, the led pin can operate as a simple switching current source to reduce power dissipation in the led drive circuitry. the ltc4263 is available in 14-pin 4mm 3mm dfn and 14-pin so packages. n ieee 802 ? .3af compliant n operation from a single 48v supply n fully autonomous operation without microcontroller n internal mosfet with thermal protection n power management works across multiple ports with simple rc network n precision inrush control with internal sense resistor n powered device (pd) detection and classi? cation n ac and dc disconnect sensing n robust short-circuit protection n pin-selectable detection backoff for midspan pses n classi? cation dependent i cut current threshold n led driver indicates port on and blinks status codes n available in 14-pin so and 4mm 3mm dfn packages n ieee 802.3af compliant endpoint/midspan pses n single-port or multi-port power injectors n power forwarders n low-port count pses n environment b pses n standalone pses single-port fully autonomous pse 4263 ta01 0.1f 100v 0.1f 0.1f 100v smaj58a led legacy midspan pwrmgt v ss v ss osc ltc4263 isolated 48v supply + C to port magnetics v dd5 enfcls sd v dd48 out out acout 1a l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. hot swap and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc4263 2 4263fe electrical characteristics absolute maximum ratings supply voltages v ss ? v dd48 ........................................... 0.3v to ?80v v dd5 ........................................ v ss ? 0.3v to v ss + 6v pin voltages and currents legacy, midspan, enfcls, pwrmgt sd , osc .................................. v ss ? 0.3v to v ss + 6v led ....................................... v ss ? 0.3v to v ss + 80v out, acout ............................................ (see note 3) (notes 1, 2) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd48 ? v ss = 48v and v dd5 not driven externally. all voltages are relative to v ss unless otherwise noted. (notes 2, 5) operating ambient temperature range ltc4263c ................................................ 0c to 70c ltc4263i ............................................. ?40c to 85c junction temperature (note 4) ............................. 125c storage temperature range ................... ?65c to 150c lead temperature (soldering, 10 sec) so ..................................................................... 300c symbol parameter conditions min typ max units power supplies v supply 48v supply voltage v dd48 ? v ss to maintain ieee compliant output l l 33 46 48 66 57 v v v uvlo_off uvlo turn-off voltage v dd48 ? v ss decreasing l 29 31 33 v v uvlo_hys uvlo hysteresis l 0.1 1 v 1 2 3 4 5 6 7 14 13 12 11 10 9 8 15 v dd5 enfcls sd v dd48 out out acout led legacy midspan pwrmgt v ss v ss osc top view de14 package 14-lead (4mm s 3mm) plastic dfn t jmax = 125c,
ltc4263 3 4263fe electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd48 C v ss = 48v and v dd5 not driven externally. all voltages are relative to v ss unless otherwise noted. (notes 2, 5) symbol parameter conditions min typ max units v ovlo_off ovlo turn-off voltage v dd48 C v ss increasing l 66 70 74 v v ovlo_hys ovlo hysteresis l 0.2 2 v v dd5 v dd5 supply voltage driven externally l 4.5 5 5.5 v v dd5 internal supply driven internally l 4.3 4.4 4.5 v i dd48 v dd48 supply current v dd5 C v ss = 5v internal v dd5 l l 1 2 2 4 ma ma i dd5 v dd5 supply current v dd5 C v ss = 5v l 12ma power mosfet r on on-resistance i = 350ma, measured from out to v ss l 1.5 2.4 3.0 1 1 i out_leak out pin leakage v out C v ss = v dd48 C v ss = 57v l 110 a r pu out pin pull-up resistance to v dd48 0v (v dd48 C v out ) 5v l 360 500 640 k 1 current control i cut overload current threshold class 0, class 3, class 4 (note 6) class 2 class 1 l l l 355 165 95 375 175 100 395 185 105 ma ma ma i lim short-circuit current limit v out C v ss = 5v v dd48 C v out = 30v l l 405 405 425 425 445 445 ma ma i fb foldback current limit v dd48 C v out = 0v (note 7) v dd48 C v out = 10v l l 30 110 60 140 120 180 ma ma i min dc disconnect current threshold l 5.2 7.5 9.8 ma i fault high speed fault current limit (note 8) l 500 650 800 ma detection i det detection current first point, v dd48 C v out = 10v second point, v dd48 C v out = 3.5v l l 235 160 255 180 275 200 a a v det detection voltage compliance v dd48 C v out , open port v dd48 C v ss = 57v l 21 v r detmin minimum valid signature resistance l 15.5 17 18.5 k 1 r detmax maximum valid signature resistance l 27.5 29.7 32 k 1 r open open circuit threshold l 500 2000 k 1 classi? cation v class classi? cation voltage v dd48 C v out , 0ma i class 50ma l 16.5 20.5 v i class classi? cation current compliance v out = v dd48 l 55 60 75 ma i tclass classi? cation threshold current class 0 C 1 class 1 C 2 class 2 C 3 (note 9) l l l 5.5 13.5 21.5 6.5 14.5 23 7.5 15.5 24.5 ma ma ma power management v pwrmgt power management pin threshold l 0.98 1 1.02 v i pwrmgt power management pin output current class 0, class 3, class 4 class 1 class 2 l l l C75.6 C19.6 C34.3 C72.3 C18.8 C32.8 C69 C17.9 C31.3 a a a ac disconnect r osc osc pin input impedance 2v (v osc C v ss ) 3v l 175 250 325 k 1 i osc osc pin output current v osc C v ss = 2v l C140 140 a f osc osc pin frequency v osc C v ss = 2v l 103 110 115 hz
ltc4263 4 4263fe symbol parameter conditions min typ max units a vacd voltage gain osc to acout 2v (v osc C v ss ) 3v l 0.95 1.0 1.05 v/v i acdmax ac disconnect output current v osc C v ss = 2v, 0v (v acout C v ss ) 4v l C1 1 ma i acdmin remain connected ac pin current v osc C v ss = 2v l 130 160 190 a v acden ac disconnect enable signal v osc C v ss , port on l 1.5 v digital interface (note 10) v oled led output low voltage i led = 10ma l 1.1 2.2 v v ild digital input low voltage midspan, pwrmgt, enfcls, sd legacy l l 0.8 0.4 v v v ihd digital input high voltage midspan, pwrmgt, enfcls, sd legacy l l 2.2 2.2 v v oz voltage of legacy pin if left floating l 1.1 1.25 1.4 v i oleg current in/out of legacy pin 0v (v legacy C v ss ) 5v l C60 60 a i flt maximum allowed leakage of external components at legacy pin in force power-on mode l C10 10 a timing characteristics t det detection time beginning to end of detection l 270 290 310 ms t detdly detection delay pd insertion to detection complete l 300 620 ms t pdc classi? cation duration l 34 37 39 ms t pon power turn-on delay end of valid detect to application of power l 135 145 155 ms t rise turn-on rise time v dd48 C v out : 10% to 90% c pse = 0.1f l 40 170 s t ovld overload/short-circuit time limit l 52 62 72 ms t ed error delay i cut fault to next detect l 3.8 4.0 4.2 s t mpdo maintain power signature (mps) disconnect delay pd removal to power removal l 320 350 380 ms t mps mps minimum pulse width pd minimum current pulse width required to stay connected (note 11) l 20 ms t dbo midspan mode detection backoff r port = 15.5k 1 l 3.0 3.2 3.4 s t disdly power removal detection delay l 0.8 0.95 1.1 s electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd48 C v ss = 48v and v dd5 not driven externally. all voltages are relative to v ss unless otherwise noted. (notes 2, 5) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to v ss unless otherwise speci? ed. note 3 : 80ma of current may be pulled from the out or acout pin without damage whether the ltc4263 is powered or not. these pins will also withstand a positive voltage of v ss + 80v. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 5 : the ltc4263 operates with a negative supply voltage. to avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. note 6: if the enfcls pin is high, i cut depends on the result of classi? cation. if enfcls pin is low, i cut reverts to its class 0 speci? cation. note 7: in order to reduce power dissipated in the switch while charging the pd, the ltc4263 reduces the current limit when v out C v ss is large. refer to the typical performance characteristics for more information. note 8: the ltc4263 includes a high speed current limit circuit intended to protect against faults. the fault protection is activated for port current in excess of i fault . after the high speed current limit activates, the short- circuit current limit (i lim ) engages and restricts current to ieee 802.3af levels. note 9: class 4 or higher classi? cation current is treated as class 3. note 10: the ltc4263 digital interface operates with respect to v ss . all logic levels are measured with respect to v ss . note 11: the ieee 802.3af speci? cation allows a pd to present its maintain power signature (mps) on an intermittent basis without being disconnected. in order to stay powered, the pd must present the mps for t mps within any t mpdo time window.
ltc4263 5 4263fe typical performance characteristics powering an ieee 802.3af pd powering a legacy pd with 220f bypass capacitor classi? cation transient response to 40ma load step overload restart delay midspan backoff with invalid pd overcurrent response time response to pd removal with ac disconnect enabled rapid response to 1 1 short rapid response to momentary 50 1 short 100ms/div v dd48 v ss 4263 g01 v out 10v/div power on classification detection phase 2 detection phase 1 25ms/div v dd48 v ss 4263 g02 v out 20v/div i out 200ma/div 0ma 400ma classification 425ma current limit load fully charged foldback 100s/div v dd48 C 18v v dd48 C 19v 4263 g06 v out 2v/div i out 20ma/div 0ma 40ma v dd48 C v ss = 48v t a = 25c 500ms/div v dd48 v ss 4263 g10 v out 10v/div i port 500ma/ div t ed 500ms/div v dd48 4263 g11 v out 2v/div t dbo r port = 15.5k 10ms/div v dd48 v ss 4263 g12 v out 20v/div i out 200ma/div 0ma 400ma t ovld load applied port off 50ms/div v dd48 v ss 4263 g13 v out 10v/div t mpdo port off pd removal 1s/div v dd48 v ss 4263 g14 v out 20v/div i port 20a/ div 0a 20a i port = current in 1 resistor applied to output of circuit on front page 1 short applied 100s/div v dd48 v ss 4263 g15 v out 20v/div i port 400ma/div 0ma 800ma current limit active 50 short applied short removed foldback current limit i port = current in 50 resistor applied to output of circuit on front page
ltc4263 6 4263fe typical performance characteristics r on vs temperature legacy pin current vs voltage current limit and foldback led pin pulldown vs load current classi? cation current compliance i dd48 dc supply current vs supply voltage with internal v dd5 i dd48 dc supply current vs supply voltage with v dd5 = 5.0v i dd5 dc supply current vs supply voltage v dd48 C v out 0 0 i out (ma) 50 150 200 250 30 35 40 45 450 4263 g03 100 5 10152025 50 300 350 400 i led load current (ma) 0 0 v led pin pulldown (v) 1 3 4 4263 g04 2 10 20 30 40 50 t a = 25c internal v dd5 v dd48 C v out (v) 04 0 i out (ma) 10 30 70 80 4263 g05 20 40 60 50 8121620 v dd48 C v ss = 48v t a = 25c v dd48 (v) 0 0 i dd48 (ma) 0.5 1.5 2.0 2.5 4263 g07 1.0 10 20 30 40 50 60 25k load with ac enabled no load t a = 25c v dd48 (v) 0 0 i dd48 (ma) 0.2 0.6 0.8 1.0 1.2 4263 g08 0.4 10 20 30 40 50 60 25k load with ac enabled no load t a = 25c v dd5 4.0 C3 i dd5 (ma) C2 0 1 2 4263 g09 C1 4.5 5.0 5.5 6.0 25k load with ac enabled no load v dd48 = 48v temperature (c) C40 C20 1.0 r on () 1.4 2.0 0 40 60 4263 g16 1.2 1.8 1.6 20 80 100 v legacy (v) 0 i legacy (a) 0 20 4 4263 g17 C20 C40 1 2 3 5 40 legacy mode force power on mode compliant mode
ltc4263 7 4263fe detect, class and turn-on timing current limit timing dc disconnect timing ac disconnect timing test timing v dd48 v out pd inserted v class port turn-on t pdc 4263 tt01 t detdly t det t pon i lim v dd48 i cut i out v out v ss 4263 tt02 t ovld i min t mpdo t mps i out 4263 tt03 v dd48 v out v ss i acout t mpdo v osc i acdmin pd removed 4263 tt04 v dd48 v out v ss
ltc4263 8 4263fe pin functions led (pin 1): port state led drive. this pin is an open drain output that pulls down when the port is powered. under port fault conditions, the led will ? ash in patterns to indicate the nature of the port fault. see the applications informa- tion section for a description of these patterns. when the ltc4263 is operated from a single 48v supply, this pin is pulsed low with a 6% duty cycle during the periods when the led should be on. this allows use of a simple inductor, diode, and resistor circuit to avoid excess heating due to the large voltage drop from v dd48 . see the applications information section for details on this circuit. legacy (pin 2): legacy detect. this pin controls whether legacy detect is enabled. if held at v dd5 , legacy detect is enabled and testing for a large capacitor is performed to detect the presence of a legacy pd on the port. see the applications information section for descriptions of legacy pds that can be detected. if held at v ss , only ieee 802.3af compliant pds are detected. if left ? oating, the ltc4263 enters force-power-on mode and any pd that generates between 1v and 10v when biased with 270a of detection current will be powered as a legacy device. this mode is useful if the system uses a differential detection scheme to detect legacy devices. warning: legacy modes are not ieee 802.3af compliant. midspan (pin 3): midspan enable. if this pin is connected to v dd5 , midspan backoff is enabled and a 3.2 second delay occurs after every failed detect cycle unless the result is open circuit. if held at v ss , no delay occurs after failed detect cycles. pwrmgt (pin 4): power management. the ltc4263 sources current at the pwrmgt pin proportional to the class of the pd that it is powering. the voltage of this pin is checked before powering the port. the port will not turn on if this pin is more than 1v above v ss . connect the pwrmgt pins of multiple ltc4263s together with a resistor and capacitor to v ss to implement power management. if power management is not used, tie this pin to v ss . v ss (pins 5, 6): negative 48v supply. pins 5 and 6 should be tied together on the pcb. osc (pin 7) oscillator for ac disconnect. if ac discon- nect is used, connect a 0.1f x7r capacitor from osc to v ss . tie osc to v ss to disable ac disconnect and enable dc disconnect. acout (pin 8): ac disconnect sense. senses the port to determine whether a pd is still connected when in ac disconnect mode. if port capacitance drops below about 0.15f for longer than t mpdo the port is turned off. if ac disconnect is used, connect this pin to the port with a series combination of a 1k resistor and a 0.47f 100v x7r capacitor. see the applications information section for more information. out (pins 9, 10): port output. if dc disconnect is used, these pins are connected to the port. if ac disconnect is used, these pins are connected to the port through a parallel combination of a 1a diode and a 500k resistor. pins 9 and 10 should be tied together on the pcb. see the applications information section for more information. v dd48 (pin 11): 48v return. must be bypassed with a 0.1f capacitor to v ss . sd (pin 12): shutdown. if held low, the ltc4263 is pre- vented from performing detection or powering the port. pulling sd low will turn off the port if it is powered. when released, a 4-second delay will occur before detection is attempted. enfcls (pin 13): enforce class current limits. if held at v dd5 , the ltc4263 will reduce the i cut threshold for class 1 or class 2 pds. if enfcls is held at v ss , i cut remains at 375ma (typ) for all classes. v dd5 (pin 14): logic power supply. apply 5v referenced to v ss , if such a supply is available, or place a 0.1f bypass capacitor to v ss to enable the internal regulator. when the internal regulator is used, this pin should only be connected to the bypass capacitor and to any logic pins of the ltc4263 that are being held at v dd5 . exposed pad (pin 15, de package only): v ss . must be connected to v ss on the pcb. the exposed pad acts as a heatsink for the internal mosfet. (dfn/so)
ltc4263 9 4263fe block diagram i det sd 12 enfcls 13 legacy smaj58a to port magnetics 2 midspan 3 v dd48 11 5v reg 500k 500k 1k 0.47f 0.1f control hot swap v dd5 14 r led led 1 pwrmgt 4 c pm r pm 0.1f to other ltc4263s bold lines indicate high current v ss 6 osc 7 out 10 5 9 acout 8 + 48v C + 5v C 4263 bd 1a v dd5 int5 ext5 4
ltc4263 10 4263fe applications information poe overview over the years, twisted-pair ethernet has become the most commonly used method for local area networking. the ieee 802.3 group, the originator of the ethernet standard, has de? ned an extension to the standard, ieee 802.3af, which allows dc power to be delivered simultaneously over the same cable used for data communication. this has enabled a whole new class of ethernet devices, in- cluding ip telephones, wireless access points, and pda charging stations which do not require additional ac wiring or external power transformers, a.k.a. wall warts. with about 13w of power available, small data devices can be powered by their ethernet connections, free from ac wall outlets. sophisticated detection and power mon- itoring techniques prevent damage to legacy data-only devices while still supplying power to newer, ethernet- powered devices over the twisted-pair cable. the device that supplies power is called the power sourcing equipment (pse). a device that draws power from the wire is called a powered device (pd). a pse is typically an ethernet switch, router, hub, or other network switching equipment that is commonly found in the wiring closets where cables converge. pds can take many forms. digital ip telephones, wireless network access points, pda or notebook computer docking stations, cell phone chargers, and hvac thermostats are examples of devices that can draw power from the network. a pse is required to provide a nominal 48v dc between either the signal pairs or the spare pairs (but not both) as shown in figure 1. the power is applied as a voltage between two of the pairs, typically by powering the cen- ter taps of the isolation transformers used to couple the differential data signals to the wire. since ethernet data is transformer coupled at both ends and is sent differen- tially, a voltage difference between the transmit pairs and the receive pairs does not affect the data. a 10base-t/ 100base-tx ethernet connection only uses two of the four pairs in the cable. the unused or spare pairs can option- ally be powered directly, as shown in figure 1, without affecting the data. 1000base-t uses all four pairs and power must be connected to the transformer center taps if compatibility with 1000base-t is required. the ltc4263 provides a complete pse solution for de- tection and powering of pd devices in an ieee 802.3af compliant system. the ltc4263 controls a single pse port that will detect, classify, and provide isolated 48v power to a pd device connected to the port. the ltc4263 senses removal of a pd with ieee 802.3af compliant ac or dc methods and turns off 48v power when the pd is disconnected. an internal control circuit takes care of system con? guration and timing. figure 1. system diagram 4263 f01 smaj58a 58v 0.1f 0.1f tx rx rx tx smaj58a 58v data pair data pair spare pair spare pair C48v supply C48v return cat 5 20 max roundtrip 0.05f max rj45 4 5 4 5 1 2 1 2 3 6 3 6 7 6 7 6 rj45 1n4002 s 4 1n4002 s 4 pse pd C48v in C48v out r class ltc4267-based pd/switcher gnd out 5mf c in 300f + C v out 0.1f 0.1f v ss out v dd48 v dd5 ltc4263
ltc4263 11 4263fe applications information ltc4263 operation signature detection the ieee 802.3af speci? cation de? nes a speci? c pair-to- pair signature resistance used to identify a device that can accept power via its ethernet connection. when the port voltage is below 10v, an ieee 802.3af compliant pd will have an input resistance of approximately 25k 1 . figure 2 illustrates the relationship between the pd sig- nature resistance and the required resistance ranges the pse must accept and reject. according to the ieee 802.3af speci? cation, the pse must accept pds with signatures between 19k 1 and 26.5k 1 and may or may not accept resistances in the two ranges of 15k 1 to 19k 1 and 26.5k 1 to 33k 1 . the black box in figure 2 represents the typical 150 1 pair-to-pair termination used in ethernet devices like a computers network interface card (nic) that cannot accept power. the ltc4263 checks for the signature resistance by forcing two test currents on the port in sequence and measuring the resulting voltages. it then subtracts the two v-i points to determine the resistive slope while removing voltage offset caused by any series diodes or current offset caused by leakage at the port (see figure 3). the ltc4263 will typically accept any pd resistance between 17k 1 and 29.7k 1 as a valid pd. values outside this range (exclud- ing open and short-circuits) are reported to the user by a code ? ashed via the led pin. the ltc4263 uses a force-current detection method in order to reduce noise sensitivity and provide a more robust detection algorithm. the ? rst test point is taken by forcing a test current into the port, waiting a short time to allow the line to settle and measuring the resulting voltage. this result is stored and the second current is applied to the port, allowed to settle and the voltage measured. the ltc4263 will not power the port if the pd has more than 5f in parallel with its signature resistor unless legacy mode is enabled. the ltc4263 autonomously tests for a valid pd connected to the port. it repeatedly queries the port every 580ms, or every 3.2s if midspan backoff mode is active (see below). if detection is successful, it performs classi? cation and power management and then powers up the port. midspan backoff ieee 802.3af requires the midspan pse to wait two seconds after a failed detection before attempting to detect again unless the port resistance is greater than 500k 1 . this requirement is to prevent the condition of an endpoint pse and a midspan pse, connected to the same pd at the same time, from each corrupting the pd signature and preventing power-on. after the ? rst corrupted detection cycle, the midspan pse waits while the endpoint pse completes detection and turns the port on. if the midspan mode of the ltc4263 is enabled by connecting the midspan pin to v dd5 , a 3.2 second delay occurs after every failed detect cycle unless the result is an open circuit. figure 2. ieee 802.3af signature resistance ranges figure 3. pd 2-point detection resistance pd pse 0 10k 15k 4263 f02 19k 26.5k 26.25k 23.75k 150 (nic) 20k 30k 33k reject accept reject first detection point second detection point valid pd 25k slope 255 180 current (a) 0v-2v offset voltage 4263 f03
ltc4263 12 4263fe applications information figure 4. classi? cation load lines classi? cation an ieee 802.3af pd has the option of presenting a classi? cation signature to the pse to indicate how much power it will draw when operating. this signature consists of a speci? c constant-current draw when the pse port voltage is between 15.5v and 20.5v, with the current level indicating the power class to which the pd belongs. per the ieee 802.3af speci? cation, there are ? ve classes and three power levels for a pd as shown in table 1. note that class 4 is presently reserved by the ieee for future use. figure 4 shows an example pd load line, starting with the shallow slope of the 25k signature resistor below 10v, then drawing the classi? cation current (in this case, class 3) between 15.5v and 20.5v. also shown is the load line for the ltc4263. it maintains a low impedance until reaching current limit at 60ma (typ). the ltc4263 will classify a port immediately after a successful detection. it measures the pd classi? cation signature current by applying 18v (typ) to the port and measuring the resulting current. the ltc4263 identi? es the three ieee power levels and stores the detected class internally for use by the power management circuitry. in addition, the ltc4263 allows selectable enforcement of ieee classi? cation power levels. with the enfcls pin high, the ltc4263 reduces the i cut current threshold if it detects class 1 or class 2, thereby insuring that pds which violate their advertised class are shut down. table 1. ieee 802.3af classi? cation, pd power consumption, and ltc4263 enforced power output ieee 802.3af class classification current maximum ieee allowable pd power ltc4263 enforced i cut threshold* class description 0 0ma to 5ma 12.95w 375ma (typ) pd does not implement classi? cation, unknown power 1 8ma to 13ma 3.84w 100ma (typ) low power pd 2 16ma to 21ma 6.49w 175ma (typ) medium power pd 3 25ma to 31ma 12.95w 375ma (typ) full power pd 4 35ma to 45ma 12.95w 375ma (typ) reserved, power as class 0 *enforced i cut active if enfcls pin is high. otherwise, i cut is 375ma (typ). v dd48 C v out 0 current (ma) 60 50 40 30 20 10 0 5101520 4263 f04 25 typical class 3 pd load line 48ma 33ma pse load line 23ma 14.5ma 6.5ma class 4 class 2 class 1 class 0 class 3 over current
ltc4263 13 4263fe applications information power management the ltc4263 includes a power management feature allowing simple implementation of power management across multiple ports driven by a single power supply. the pwrmgt pins of all ltc4263 devices are tied together along with an rc network to prevent over-allocation of power in a multi-port system. immediately following classi? cation, the ltc4263 performs a power management check to ensure power is available to supply the newly classed pd. the allocated power is represented by the voltage on the shared pwrmgt node and the ltc4263 checks the allocated power by measur- ing this voltage. if the pwrmgt voltage is less than 1v, there is power available and the power needs of the new pd are added to the already allocated power on the node. to allocate power, a current proportional to the power needs for the new pd is sourced out of the pwrmgt pin (table 2). table 2. ltc4263 power management ieee 802.3af class pse output power required ltc4263 pwrmgt current 0, 3, 4 15.4w C72.3a 2 7w C32.8a 1 4w C18.8a for multiple ltc4263s implementing power management, the pwrmgt pins are connected together and to a rc network connected to v ss as shown in figure 5. the value of r pm represents the full load output capability of the system power supply (p full_load ). select a 1% resistor to set the full load output power using the following formula: r kw p pm full load = 213 1 ? _ the ltc4263 power management uses pulse width modulation to set the power requirements of each pd. capacitor c pm is used as a lowpass ? lter to generate the average power requirement for all pds in the system. set c pm to 1f. if power management is not used, tie pwrmgt to v ss . when additional current is added to the pwrmgt node, the voltage rises toward the 1v threshold. after adding current, the ltc4263 veri? es that the power supply is not over-allocated by verifying the node voltage remains below 1v. if the voltage is below 1v, the ltc4263 proceeds to power the port. if over 1v, the current is removed from the node, port powering is aborted, and the ltc4263 goes back into detection mode. figure 5. pwrmgt pin connections pwrmgt v ss ltc4263 pwrmgt v ss ltc4263 pwrmgt v ss ltc4263 pwrmgt v ss v ss ltc4263 4263 f05 c pm 1f r pm
ltc4263 14 4263fe applications information power control the primary function of the ltc4263 is to control the delivery of power to the pse port. in order to meet ieee 802.3af requirements and provide a robust solution, a variety of current limit and current monitoring functions are needed, as shown in figure 6. all control circuitry is integrated and the ltc4263 requires no external mosfet, sense resistor, or microcontroller to achieve ieee compliance. the ltc4263 includes an internal mosfet for driving the pse port. the ltc4263 drives the gate of the internal mosfet while monitoring the current and the output volt- age at the out pin. this circuitry couples the 48v input supply to the port in a controlled manner that satis? es the pds power needs while minimizing disturbances on the 48v backplane. figure 6. current thresholds and current limits port overload a pse port is permitted to supply up to 15.4w continuously and up to 400ma (i cut ) for up to 75ms (t ovld ) when in overload. per the ieee 802.3af speci? cation, the pse is required to remove power if a port stays in an overload condition. the ltc4263 monitors port current and removes port power if port current exceeds 375ma (typ) for greater than 62ms (typ). port inrush and short-circuit the ieee 802.3af standard lists two separate maximum current limits, i inrush and i lim , that a pse must implement. i inrush refers to current at port turn-on and i lim is the maximum allowable current in the case of a short after the port is powered. because the ieee speci? cation calls out identical values, the ltc4263 implements both as a single current limit referred to as i lim . when 48v power is applied to the port, the ltc4263 is designed to power-up the pd in a controlled manner without causing transients on the input supply. to accomplish this, the ltc4263 implements inrush current limit. at turn-on, current limit will allow the port voltage to quickly rise until the pd reaches its input turn-on threshold. at this point, the pd begins to draw current to charge its bypass capacitance, slowing the rate of port voltage increase. if at any time the port is shorted or an excessive load is applied, the ltc4263 limits port current to avoid a haz- ardous condition. the current is limited to i lim for port voltages above 30v and is reduced for lower port voltages (see the foldback section). inrush and short-circuit cur- rent limit are allowed to be active for 62ms (typ) before the port is shut off. port fault if the port is suddenly shorted, the internal mosfet power dissipation can rise to very high levels until the short-circuit current limit circuit can respond. a separate high speed current limit circuit detects severe fault conditions ( i out > 650ma (typ) ) and quickly turns off the internal mosfet if such an event occurs. the circuit then limits current to i lim while the t ovld timer increments. during a short-circuit, i lim will be reduced by the foldback circuitry. t ovld timing for overload, inrush, and short-circuit conditions, the ieee 802.3af standard limits the duration of these events to 50ms-75ms. the ltc4263 includes a 62ms (typ) t ovld timer to monitor overload conditions. the timer is incre- mented whenever current greater than i cut ? ows through the port. if the current is still above i cut when the t ovld timer expires, the ltc4263 will turn off power to the port and ? ash the led. in this situation, the ltc4263 waits four seconds and then restarts detection. if the overload port current 0ma 100ma dc disconnect (i min ) limit (i lim ) cut (i cut ) 200ma 300ma 400ma 500ma current limit port off in t ovld dc disconnect port off in t mpdo 4263 f07 normal operation
ltc4263 15 4263fe applications information condition is removed before the t ovld timer expires, the port stays powered and the timer is reset. foldback foldback is designed to limit power dissipation in the ltc4263 during power-up and momentary short-circuit conditions. at low port output voltages, the voltage across the internal mosfet is high, and power dissipa- tion will be large if signi? cant current is ? owing. foldback monitors the port output voltage and reduces the i lim current limit level for port voltages of less than 28v, as shown in figure 7. figure 7. current limit foldback thermal protection the ltc4263 includes thermal overload protection in order to provide full device functionality in a miniature package while maintaining safe operating temperatures. several factors create the possibility for very large power dissipation within the ltc4263. at port turn-on, while i lim is active, the instantaneous power dissipated by the ltc4263 can be as high as 12w. this can cause 40oc or more of die heating in a single turn-on sequence. similarly, excessive heating can occur if an attached pd repeatedly pushes the ltc4263 into i lim by drawing too much cur- rent. excessive heating can also occur if the v dd5 pin is shorted or overloaded. the ltc4263 protects itself from thermal damage by monitoring die temperature. if the die temperature exceeds the overtemperature trip point, the ltc4263 removes port power and shuts down all functions including the internal 5v regulator. once the die cools, the ltc4263 waits four seconds, then restarts detection. dc disconnect the dc disconnect circuit monitors port current whenever power is on to detect continued presence of the pd. ieee 802.3af mandates a minimum current of 10ma that the pd must draw for periods of at least 75ms with optional dropouts of no more than 250ms. the t mpdo disconnect timer increments whenever port current is below 7.5ma (typ). if the timer expires, the port is turned off and the ltc4263 waits 1.5 seconds before restarting detection. if the undercurrent condition goes away before t mpdo ( 350ms (typ) ) , the timer is reset to zero. the dc disconnect circuit includes a glitch ? lter to prevent noise from falsely resetting the timer. the current must be present for a period of at least 20ms to guarantee reset of the timer. to enable dc disconnect, tie the osc pin to v ss . ac disconnect ac disconnect is an alternate method of sensing the pres- ence or absence of a pd by monitoring the port impedance. the ltc4263 forces an ac signal from an internal sine wave generator on to the port. the acout pin current is then sampled once per cycle and compared to i acdmin . like dc disconnect, the ac disconnect sensing circuitry controls the t mpdo disconnect timer. when the connection impedance rises due to the removal of the pd, ac peak current falls below i acdmin and the disconnect timer increments. if the impedance remains high (ac peak current remains below i acdmin ), the disconnect timer counts to t mpdo and the port is turned off. if the impedance falls, causing ac peak current to rise above i acdmin for two consecutive samples before the maximum count of the disconnect timer, the timer resets and the port remains powered. the ac disconnect circuitry senses the port via the acout pin. connect a 0.47f 100v x7r capacitor (c det ) and a 1k 1 resistor (r det ) from the detect pin to the port output as shown in figure 8. this provides an ac path for sensing the port impedance. the 1k 1 resistor, r det , limits current ? owing through this path during port power-on and power-off. an ac blocking diode (d ac ) is inserted between the out pin and the port to prevent the ac signal from v dd48 C v out (v) 0 i lim (ma) 300 400 500 40 4263 f07 200 100 0 51015 20 25 30 35 45 50
ltc4263 16 4263fe applications information being shorted by the ltc4263s power control mosfet. the 500k resistor across d ac allows the port voltage to decay after disconnect occurs. sizing of capacitors is critical to ensure proper function of ac disconnect. c pse (figure 8) controls the connection impedance on the pse side. its capacitance must be kept low enough for ac disconnect to be able to sense the pd. on the other hand, c det has to be large enough to pass the signal at 110hz. the recommended values are 0.1f for c pse and 0.47f for c det . the sizes of c pse , c det , and r det are chosen to create an economical, physically compact and functionally robust system. moreover, the complete power over ethernet ac disconnect system (pse, transformers, cabling, pd, etc.) is complex; deviating from the recommended values of c det , r det and c pse is strongly discouraged. contact the linear technology applications department for additional support. internal 110hz ac oscillator the ltc4263 includes onboard circuitry to generate a 110hz (typ), 2v p-p sine wave on its osc pin when a 0.1f capacitor is connected between the osc pin and v ss . this sine wave is synchronized to the controller inside the ltc4263 and should not be externally driven. tying the osc pin to v ss shuts down the oscillator and enables dc disconnect. power-on reset and reset/backoff timing upon start-up, the ltc4263 waits four seconds before starting its ? rst detection cycle. depending on the re- sults of this detection it will either power the port, repeat detection, or wait 3.2 seconds before attempting detection again if in midspan mode. the ltc4263 may be reset by pulling the sd pin low. the port is turned off immediately and the ltc4263 sits idle. after sd is released there will be a 4-second delay before the next detection cycle begins. v dd5 logic-level supply the v dd5 supply for the ltc4263 can either be supplied externally or generated internally from the v dd48 supply. if supplied externally, a voltage between 4.5v and 5.5v should be applied to the v dd5 pin to cause the internal regulator to shut down. if v dd5 is to be generated inter- nally, the voltage will be 4.4v (typ) and a 0.1f capacitor should be connected between v dd5 and v ss . do not connect the internally generated v dd5 to anything other than a bypass capacitor and the logic control pins of the same ltc4263. led flash codes the ltc4263 includes a multi-function led driver to inform the user of the port status. the led is turned on when the port is connected to a pd and power is applied. if the port is not connected or is connected to a non-powered device with a 150 1 or shorted termination, the port will not be powered and the led will be off. for other port conditions, the ltc4263 blinks a code to communicate the status to the user as shown in table 3. one ? ash indicates low signature resistance, two ? ashes indicates high resistance, ? ve ? ashes indicates an overload fault, and nine ? ashes indicates that power management is preventing the port from turning on. figure 8. ltc4263 using ac disconnect 4263 f08 0.1 f 100v 0.1 f nc 0.1 f c det 0.47 f x7r, 100v c pse 0.1 f x7r, 100v smaj58a led legacy midspan pwrmgt v ss v ss osc acout ltc4263 d ac cmlsh05-4 500k isolated 48v supply + C r det 1k 1a v dd5 enfcls sd v dd48 out out
ltc4263 17 4263fe applications information when active, the led ? ash codes are repeated every 1.2 seconds. the duration of each led ? ash is 75ms. multiple led ? ashes occur at a 300ms interval. the ltc4263 includes a feature for ef? ciently driving the led from a 48v power supply without the wasted power caused by having to drop over 45v in a current limit resistor. when operating the v dd5 supply internally, the ltc4263 drives the led pin with a 6% duty cycle pwm signal. this allows use of the simple led drive circuit in figure 9 to minimize power dissipation. the modulation frequency of the led drive is 28khz, making the on period 2.2s. during the 2.2s that the led pin is pulled low, cur- rent ramps up in the inductor, limited by r led . diode d2 completes the circuit by allowing current to circulate while the led pin is open circuit. since current is only drawn from the power supply 6% of the time, power dissipation is substantially reduced. when v dd5 is powered from an external supply, the pwm signal is disabled and the led pin will pull down continu- ously when on. in this mode, the led can be powered from the 5v supply with a simple series resistor. ieee 802.3af compliance and external component selection this section discusses the other elements that go along with the ltc4263 to make an ieee 802.3af compliant pse. the ltc4263 is designed to control power delivery in ieee 802.3af compliant power sourcing equipment. because proper operation of the ltc4263 also depends on external components and power sources like the 48v supply, using the ltc4263 in a pse does not in itself guarantee ieee 802.3af compliance. to ensure a compliant pse design, it is recommended to adhere closely to the example ap- plication circuits provided. for further assistance contact the linear technology applications department. figure 9. led drive circuit with single 48v supply table 3. port status and led flash codes port status led flash code flash pattern non-powered device 0 1 < r port < 200 1 off led off port open r port > 1m 1 off led off port on 25k 1 on led on low signature resistance 300 1 < r port < 15k 1 1 flash high signature resistance 33k 1 < r port < 500k 1 2 flashes port overload fault 5 flashes power management allocation exceeded 9 flashes v dd48 d1 10mh, 21ma coilcraft ds1608c-106 d2 bas19 v dd5 r led 1k v dd48 led v ss ltc4263 4263 f09 0.1 f
ltc4263 18 4263fe applications information common mode chokes both non-powered and powered ethernet connections achieve best performance for data transfer and emi when a common mode choke is used on each port. for cost reduction reasons, some designs share a common mode choke between two adjacent ports. this is not recommended. sharing a common mode choke between two ports couples start-up, disconnect and fault transients from one port to the other. the end result can range from momentary noncompliance with ieee 802.3af to intermittent behavior and even to excessive voltages that may damage circuitry in both the pse and pd connected to the port. transient suppressor diode ieee 802.3af power over ethernet is a challenging hot swap ? application because it must survive unintentional abuse by repeated plugging in and out of devices at the port. ethernet cables could potentially be cut or shorted together. consequently, the pse must be designed to handle these events without damage. the most severe of these events is a sudden short on a powered port. what the pse sees depends on how much cat-5 cable is between it and the short. if the short occurs on the far end of a long cable, the cable inductance will prevent the current in the cable from increasing too quickly and the ltc4263 built-in short-circuit protection will control the current and turn off the port. however, the high current along with the cable inductance causes a large ? yback voltage to appear across the port when the mosfet is turned off. in the case of a short occurring with a minimum length cable, the instantaneous current can be extremely high due to the lower inductance. the ltc4263 has a high speed fault current limit circuit that shuts down the port in 20s (typ). in this case, there is lower inductance but higher current so the event is still severe. a transient suppressor is required to clamp the port voltage and prevent damage to the ltc4263. an smaj58a or equivalent device works well to maintain port voltages within a safe range. a bidirectional transient suppressor should not be used. good board layout places the transient suppressor between the port and the ltc4263 to enhance the protective function. if the port voltage reverses polarity and goes positive, the out pin can be overstressed because this voltage is stacked on top of the 48v supply. in this case, the transient suppressor must clamp the voltage to a small positive value to protect the ltc4263 and the pse capacitor. component leakages across the port can have an adverse affect on ac disconnect and even affect dc disconnect if the leakage becomes severe. the smaj58a is rated at less than 5a leakage at 58v and works well in this application. there is a potential for stress induced leakage, so suf? cient margins should be used when selecting transient suppressors for these applications. capacitors sizing of both the c det and c pse capacitors is critical for proper operation of the ltc4263 ac disconnect sensing. see the ac disconnect section for more information. note that many ceramic capacitors have dramatic dc voltage and temperature coef? cients. use 100v or higher rated x7r capacitors for c det and c pse , as these have reduced voltage dependence while also being relatively small and inexpensive. bypass the 48v supply with a 0.1f, 100v capacitor located close to the ltc4263. the v dd5 supply also requires a 0.1f bypass capacitor.
ltc4263 19 4263fe applications information fuse while the ltc4263 does not require a fuse for proper operation or for compliance with ieee 802.3af, some safety requirements state that the output current must be limited to less than 2a in less than 60 seconds if any one component fails or is shorted. since the ltc4263 is the primary current limiter, its failure could result in excess current to the port. to meet these safety requirements, a fuse can be placed in the positive leg of the port. the fuse must be large enough that it will pass at least 450ma when derated for high temperature but small enough that it will fuse at less than 2a at cold temperature. this requirement can usually be satis? ed with a 1a fuse or ptc. placing the fuse between the rj-45 connector and the ltc4263 and its associated circuitry provides additional protection for this circuitry. consult a safety requirements expert for the application speci? c requirements. power supply poor regulation on the 48v supply can lead to noncompliance. the ieee speci? cation requires a pse output voltage between 44v and 57v. when the ltc4263 begins powering an ethernet port, it controls the current through the port to minimize disturbances on v ss . however, if the v ss supply is underdamped or otherwise unstable, its voltage could go outside of the ieee-speci? ed limits, causing the pse to be noncompliant. this scenario can be even worse when a pd is unplugged because the current can drop immediately to zero. in both cases the port voltage must always stay between 44v and 57v. beyond this, the ieee 802.3af speci? cation places speci? c ripple, noise and load regulation requirements on the pse. disturbances on v ss can also adversely affect detection, classi? cation and ac disconnect sensing. for these reasons, proper bypassing and stability of the v ss supply is important. another problem that can affect the v ss supply is insuf? cient power, leading to the supply voltage dropping out of the speci? ed range. the 802.3af speci? cation states that if a pse powers a pd it must be able to provide the maximum power level requested by the pd based on the pds classi? cation. the speci? cation does allow a pse to choose not to power a port, typically because the pd requires more power than the pse has available to deliver. if a pse is built with a v ss supply not capable of delivering full power to all ports, it is recommended to use the ltc4263 power management feature to prevent ports from being turned on when there is insuf? cient power. because the speci? cation also requires the pse to supply an inrush current of 400ma at up to a 5% duty cycle, the v ss supply capability should be at least a few percent higher than the maximum total power the pse needs to supply to the pds. isolation the ieee 802.3af standard requires ethernet ports to be electrically isolated from all other conductors that are user accessible. this includes the metal chassis, other connectors, and the ac power line. environment a isolation is the most common and applies to wiring within a single building serviced by a single ac power system. for this type of application, the pse isolation requirement can be met with the use of a single, isolated 48v supply powering several ltc4263 ports. environment b, the stricter isolation requirement, is for networks that cross an ac power distribution boundary. in this case, electrical isolation must be maintained between each port in the pse. the ltc4263 can be used to build a multi-port environment b pse by powering each ltc4263 from a separate, isolated 48v supply. in all pse applications, there should be no user accessible connections to the ltc4263 other than the rj-45 port.
ltc4263 20 4263fe typical applications three port midspan pse with power management set for 30w 14 12 2 3 13 5 6 4263 ta02 0.1f midspan in v dd5 sd legacy midspan enfcls v ss v ss ltc4263 isolated 48v acout out out v dd48 led pwrmgt osc 1 2 3 4 5 6 7 8 midspan out rj45 rj45 1 2 3 4 5 6 7 8 8 10 9 11 1 4 7 smaj58a 0.1 f 100v 1k 0.1 f 100v 14 12 2 3 13 5 6 0.1f midspan in v dd5 sd legacy midspan enfcls v ss v ss ltc4263 acout out out v dd48 led pwrmgt osc v dd48 led pwrmgt osc 1 2 3 4 5 6 7 8 midspan out rj45 rj45 1 2 3 4 5 6 7 8 8 10 9 11 1 4 7 smaj58a 0.1 f 100v 1k 0.1 f 100v 14 12 2 3 13 5 6 0.1f midspan in v dd5 sd legacy midspan enfcls v ss v ss ltc4263 acout out out r pm 7.15k 1% 1 2 3 4 5 6 7 8 midspan out rj45 rj45 1 2 3 4 5 6 7 8 8 10 9 11 1 4 7 smaj58a 0.1 f 100v 1k 0.1 f 100v c pm 1 f
ltc4263 21 4263fe package description de package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1708 rev b) 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1.70 0.05 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de14) dfn 0806 rev b pin 1 notch r = 0.20 or 0.35 45 chamfer 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 0.25 0.05 0.50 bsc 3.30 0.05 3.30 0.10 0.50 bsc
ltc4263 22 4263fe package description s package 14-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) 1 n 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 14 13 .337 ? .344 (8.560 ? 8.738) note 3 .228 ? .244 (5.791 ? 6.197) 12 11 10 9 5 6 7 n/2 8 .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0 ? 8 typ .008 ? .010 (0.203 ? 0.254) s14 0502 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc .245 min n 1 2 3 n/2 .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
ltc4263 23 4263fe information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number e 6/10 replaced figure 3 in applications information section 11 (revision history begins at rev e)
ltc4263 24 4263fe linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0610 rev e ? printed in usa related parts typical application part number description comments ltc1737 high power isolated flyback controller sense output voltage directly from primary-side winding ltc3803 current mode flyback dc/dc controller in thinsot tm 200khz constant-frequency, adjustable slope compensation, optimized for high input voltage applications ltc4257 ieee 802.3af pd interface controller 100v 400ma internal switch, programmable classi? cation ltc4257-1 ieee 802.3af pd interface controller 100v 400ma dual current limit ltc4258 quad ieee 802.3af power over ethernet controller dc disconnect only ltc4259a-1 quad ieee 802.3af power over ethernet controller with ac disconnect ltc4267 ieee 802.3af pd interface with switcher integrated current mode switching regulator complete single-port endpoint pse with integrated rj45 l1 10mh, 21ma ds1608c-106 coilcraft led1 ln1351c-tr grn 4263 ta03 c1 0.1 f d5 cmlsho5-4 r6 1k 22nf 75 rd + phy rd C 2kv 1000pf jko-0044 pulse out to cable 1:1 v dd5 sd legacy midspan enfcls v ss v ss 14 12 2 3 13 5 6 ltc4263 u1 isolated 48v acout out out v dd48 led pwrmgt osc 8 10 9 11 1 4 7 td + ct j1 td C vc1a vc1b vc2a vc2b 2 9 1 7 8 5 10 6 11 tx + tx C rx + rx C 1:1 d2 smaj58a c4 0.1 f 100v 22nf 75 22nf 75 22nf 4 6 3 2 1 5 7 8 75 r2 1k r5 510k c7, 0.47 f 100v, x7r c5 0.1 f d1 bas19 c3 0.1 f 100v f1 1a

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